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Best Practices for Running the Conference Review Process Based on USENIX ATC 2018

I got the opportunity to participate in the review process as a program committee member for USENIX ATC 2018. USENIX ATC is a big conference in term of submissions: this year, it received more than 400 complete submissions. To handle such a huge load on reviewing, the chairs had purposedly doubled the number of program committee members to be 70 this year. Still, it requires a careful planning to run the paper reviewing process smoothly.

SPDK on Samsung 960 EVO NVMe SSD

Today, I started to play with Intel SPDK with a 250GB Samsung 960 EVO NVMe SSD. I was thinking that using SPDK might lead to better performance, than through traditional block device interface. However, using fio with 4KiB random read requests at the queue depth equal to 1, as it turned out, the difference is rather small.

Metric SPDK /dev/nvme0n1
IOPS 12.8 K 11.6 K
slat 0.18 usec
clat 77.73 usec 84.19 usec
lat 77.91 usec 84.32 usec

slat, clat and lat are average submission latency, submission to IO completion latency and total IO latency. As we can see, this device still have a quite high read latency. The latest Intel Optane DC P4800X SSDs can achieve 10 us read latency, with 550 K IOPS. For this Samsung device, software overhead seems still fine. It would be really interesting to test out for the Intel Optane PC4800X SSDs though.

Great Books and Papers

Books

  • A Philosophy of Software Design, John Ousterhout, Professor at Stanford University
  • The Innovator’s Dilemma, Clayton Christensen
  • UNIX - A History and a Memorior, Brian Kernighan, Professor at Princeton University
  • HOW NOT TO BE WRONG, Jordan Ellenberg, Professor of Mathematics at the University of Wisconsin-Madison
  • THINKING, FAST AND SLOW, Daniel Kahneman, Professor of Psychology Emeritus at Princeton University
  • China’s Economy, Arthur R. Kroeber

Papers

There are some papers that are so well written that I really enjoyed reading them. Here is a list of them.

NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems

This paper introduces a new B+ tree variation that is optimized for NVM by reducing consistency cost from memory fence and cacheline flush operations.

  1. Consistency is guaranteed only for leaf nodes. Internal nodes are re-built from leaf nodes.
  2. Elements in leaf nodes are not sorted. A log-structure is used for leaf nodes to remove the need for frequent synchronization. Only appends are added to a leaf node. This also increases concurrency. When a leaf node becomes full, a GC is triggered for cleaning and consolidation.
  3. Internal nodes are managed using arrays, rather than pointed based data structures.

Reflection After Dissertation Defense

After six years in the PhD program, since August 2009, I finally defended my dissertation today. I feel grateful that I finally make it. I do think I am one of the luck ones: I have a really nice adviser and he gives me strong support to do research in areas which I am interested in. I feel grateful for all the help I have received from my advisor, committee members, office mates and co-workers. The journey would be much challenging if I did it alone. Thank you all!

Sketch Data Structures

Tonight, I went to attend a local meetup event. The talk was given by a faculty from my own department, Jeff Phillips, an assistant professor working in the area of big data analysis. The topic of his talk is about sketch data structure - data structures which uses a much smaller amount of memory to summarize the represented data.This is a cool technique and I am very interested to learn more.